The present disclosure relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch and a method for manufacturing the same.
Stacked semiconductor packages are packages that are manufactured by using a three-dimensional (3D) chip stacking technique included in a highly integrated packaging technology.
Examples of a method of stacking semiconductor chips based on the 3D chip stacking technique include a chip to chip (C2C) method, a chip to wafer (C2W) method, a wafer to wafer (W2 W) method, etc. Here, the C2C stacking technique is relevant to a method of stacking a semiconductor chip and a semiconductor chip, and the C2W stacking technique is relevant to a method of stacking a semiconductor chip and a semiconductor wafer.
Also, the W2 W stacking technique is relevant to a method of stacking a semiconductor wafer and a semiconductor wafer. Considering productivity, the C2W stacking technique or the W2 W stacking technique where wafers and chips are stacked by a wafer unit is better than the C2C stacking technique where chips are stacked by a chip unit.
With the high-performance and miniaturization trend of electronic devices, the number of input/output (I/O) terminals of a semiconductor package has considerably increased, and thus, a bump pitch that electrically connects a top semiconductor package and a bottom semiconductor package of a stacked semiconductor package is on a fining trend.
As described above, as a bump pitch becomes narrower, a defect where a bump bridge is formed between adjacent bumps can occur, and for this reason, there is a limitation in implementing a stacked semiconductor package including a fine bump pitch.